Senior SystemC/TLM2 Modeler

LanceSoft, Inc. United State
Remote
This Job is No Longer Active This position is no longer accepting applications
AI Summary

Design and develop SystemC/TLM2 models for memory controllers, peripherals, and interconnects. Collaborate with cross-functional teams to integrate models into system-level designs. Optimize model performance and create comprehensive documentation.

Key Highlights
Develop, enhance, and maintain SystemC/TLM2 models
Collaborate with cross teams to integrate models
Optimize model performance and create documentation
Technical Skills Required
SystemC C++ Transaction-Level Modeling (TLM) Performance modeling Architecture exploration UVM verification SV C/C++ Perforce Git
Benefits & Perks
$55.00/hr to $60.00/hr salary
Hybrid or fully remote work option
Flexible salary based on experience

Job Description


Pay Rate: $55.00/hr to $60.00/hr on W2 (We can extend 5 to 10 dollar more depending on the experience)

Location: Preference is Hybrid but Open to a fully remote candidate.


• Minimum 5 years of experience in SystemC.

• Recent and relevant experience with SystemC.

• Resume includes hands-on modeling projects using SystemC.

• Familiarity with Transaction-Level Modeling (TLM) concepts and implementation.

• Experience in performance modeling and architecture exploration using SystemC.

• Ability to work with C++ integration, since SystemC is built on C++.

• Exposure to verification methodologies in SystemC (e.g., testbench creation, simulation).

• Knowledge of modeling at different abstraction levels (e.g., behavioral, RTL, TLM).


JOB DUTIES:

  • Develop, enhance, and maintain SystemC/TLM2 models for memory controllers, peripherals, and interconnects, ensuring they accurately simulate the behavior and performance characteristics of the hardware.
  • Collaborate with cross teams to integrate models into tools used for system-level designs, ensuring proper functionality and performance.
  • Identify bottlenecks and performance issues within models and work to optimize their performance to meet design specifications.
  • Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging.
  • Create clear and comprehensive documentation for models, including usage guidelines and design specifications.


Deliverables:

Cycle approximate performance models

SV/UVM Functional and Performance Verification


EXPERIENCE AND EDUCATION:

• B.E/M.E/M.Tech or B.S/M.S in EE/CSE with over 5 years of recent hands-on experience in SystemC and TLM2 modeling

• Proficiency in C/C++ programming.

• Understanding of memory controller architectures, including DDR, LPDDR, and other relevant standards is preferred.

• UVM verification experience is preferred.

• Experience with debuggers and handling complex projects.

• Experience working in geographically dispersed teams; must be a strong team player.

• Knowledge of system-level architecture including buses like AXI/AHB and bridges is a plus.

• Familiarity with version control systems such as Perforce or Git.


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