Senior Design Verification Engineer

IC Resources • United Kingdom
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AI Summary

Join a fast-growing startup as a Senior Design Verification Engineer to verify highly secure designs and develop security-critical technologies. Collaborate with experienced engineers in a high-trust environment. Influence verification methodologies and strategies.

Key Highlights
Verify highly secure designs
Develop Python-based tools and automation
Influence verification methodologies and strategies
Key Responsibilities
Build and extend UVM testbenches
Develop Python-based tools and automation
Influence verification methodologies and strategies
Technical Skills Required
UVM Python SystemVerilog Assertions (SVA)
Benefits & Perks
Competitive base salary
Share options
Fully remote role
Visa sponsorship available

Job Description


I am seeking a Senior Design Verification Engineer to join an established and fast-growing startup as it enters its next phase of growth. With a team of nearly 100 people, this company is at the forefront of post-quantum cryptography, developing security-critical technologies with global impact.


You will play a key role in verifying highly secure designs, working closely with experienced engineers in a collaborative, high-trust environment.


What You’ll Be Doing

As part of the verification team, you will:

  • Build and extend UVM testbenches to verify cryptographic IP and subsystem designs
  • Develop Python-based tools and automation to improve verification efficiency and productivity
  • Apply formal verification techniques in creative and effective ways


Beyond Hands-on Verification, You Will Also

  • Influence and define verification methodologies and strategies
  • Architect testbenches using UVM and formal-based approaches
  • Define verification plans, functional coverage models, and test strategies at block and subsystem level
  • Lead verification for IPs or subsystems, including effort estimation, scheduling, task allocation, and progress reporting
  • Drive coverage closure and sign-off quality across complex designs
  • Mentor junior engineers and help raise the overall capability of the team


Required Experience

  • Strong background in UVM-based verification at IP and subsystem levels
  • Proven experience building UVM testbenches from scratch
  • Proficiency in Python for verification automation
  • Solid experience with SystemVerilog Assertions (SVA)
  • A minimum of 4 years experience.


What’s On Offer

  • Competitive base salary plus share options
  • Opportunity to help build something from the ground up in a growing, mission-driven company
  • Fully remote role (must be based at a UK address)
  • Visa sponsorship available


This role will suit someone who thrives in small, collaborative teams, communicates clearly, and is passionate about delivering high-quality verification for security-critical systems.


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