Senior FPGA Engineer

Senior FPGA Engineer

• £45,000 – £65,000 + excellent bens and development opportunities
• We can offer relocation and visa support for overseas candidates
• Rochester, Kent (4 days p/w onsite)

As a Senior FPGA Engineer, you will be a member of a dedicated team of experts responsible for the design and verification of Field Programmable Gate Arrays (FPGAs).

You will develop digital and mixed-signal electronic solutions for products such as augmented reality displays, head-up displays, mission computers, fly-by-wire flight controls, active inceptors, and other associated safety-critical technology.

This is a place where you’ll be able to make a real difference. You’ll be part of an inclusive culture that values diversity, rewards integrity, and merit, and where you’ll be empowered to fulfil your potential.

You’ll be part of the development and supply of products across a diverse mix of commercial and military platforms; Head Up and Head Worn Displays, Safety Critical Pilot Control and Flight Control Systems.

What you’ll be doing:

• Providing technical expertise in the development and delivery of PLD/FPGA development, from requirements development, concept and detailed design, coding VHDL, synthesis and through to complete verification
• Understanding of PLD/FPGA design constraints & impacts on other engineering disciplines
• Managing own tasks & the tasks of others within schedules and budgets to meet programme needs
• Delivering design artefacts in support of company standards
• Coaching & developing the skills of junior team members

Your skills and experiences:

Essential:

• Degree/HND in electronics engineering or an equivalent qualification
• Proven knowledge of FPGA technologies, development tools and techniques
• Experience of working in an FPGA development team

Desirable:

• Experience of digital hardware design for FPGA using VHDL
• Experience and knowledge of video processing and control law algorithms
• Working knowledge and experience of UVM (Universal Verification Methodology) constrained random verification