AI Summary
Design and architect the RTL for a high-performance AI accelerator, owning digital blocks from microarchitecture to silicon. Implement synthesizable SystemVerilog, optimize PPA targets, and collaborate across DV, PD, and DFT. Requires 5+ years of complex digital design experience with strong RTL, synthesis, and timing expertise.
Key Highlights
End-to-end ownership of digital blocks (compute datapath, memory, interconnect, control logic) for an AI accelerator
Translate microarchitecture specs into synthesizable, timing-clean RTL with PPA optimization
Collaborate with verification, physical design, and DFT teams from RTL to tapeout
Key Responsibilities
Design and implement RTL for compute datapath, memory subsystems, on-chip interconnect, and control logic
Define microarchitecture trade-offs (pipelining, datapath vs. control, clock/power gating) for high-performance, low-power designs
Translate architectural specs into synthesizable RTL, ensuring PPA targets are met via SDC, STA, and lint signoff
Collaborate with verification engineers on block-level testing, physical design for synthesis/timing closure, and DFT for testability
Debug and validate designs across simulation, emulation, and post-silicon bring-up
Develop and leverage AI-assisted tool flows to accelerate design and verification processes
Technical Skills Required
Benefits & Perks
Equity grant per company guidelines
Medical, dental, and vision insurance
401(k) retirement plan with standard PTO
Nice to Have
AI/ML accelerator or high-performance compute datapath design experience
Low-power techniques (UPF) and high-speed interfaces (HBM, PCIe, SerDes)
Experience with advanced nodes (7nm or better) or RISC-V/CPU design
FPGA prototyping knowledge
Job Description
About The Role
Design the RTL that defines our AI accelerator. You'll architect and implement the digital blocks — compute datapath, memory subsystem, on-chip interconnect, and control logic — from microarchitecture spec through synthesis-ready, timing-clean RTL, and own those blocks end-to-end with architecture, DV, physical design, and DFT all the way to silicon.
What You'll Do:
- Own RTL design of digital blocks/subsystems for our accelerator — microarchitecture definition, SystemVerilog implementation, and integration
- Translate architectural specs into efficient, synthesizable RTL that meets power/performance/area (PPA) targets
- Drive microarchitecture trade-offs — pipelining, datapath vs. control, clock/power gating — for high-performance, low-power design
- Partner with DV on verification, PD on synthesis/timing/floorplan closure, and DFT on testability
- Own block-level quality: synthesis, timing/constraints (SDC, STA), lint, and CDC signoff
- Contribute to architecture definition and design reviews; debug across simulation, emulation, and post-silicon bring-up
- Use and develop AI-assisted tool flows to accelerate design and verification
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- Strong digital-design fundamentals and expert Verilog/SystemVerilog RTL
- 5+ years designing complex digital blocks/SoCs taken to silicon
- Solid microarchitecture skills — pipelining, datapath/control, FIFOs, arbitration, memory subsystems, on-chip interconnect/NoC
- Synthesis & timing awareness — writing synthesizable RTL, SDC constraints, STA, clock/power gating, CDC, lint
- Demonstrated collaboration with DV, PD, and DFT across the full RTL2GDS flow to tapeout
- Scripting (Python/Tcl/) for design automation
- (Optional) AI/ML accelerator or high-performance compute-datapath design; low-power techniques (UPF); high-speed interfaces (HBM, PCIe, SerDes); advanced nodes (7nm or better); RISC-V/CPU design; FPGA prototyping
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Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.
Visa Sponsorship
DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status.
Export Controls
Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.
Equal Opportunity
DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.
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California pay range: $250,000 USD - $375,000 USD
Compensation
Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.
Visa Sponsorship
DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status.
Export Controls
Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.
Equal Opportunity
DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.
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